1. Field of the Invention
The present invention relates generally to semiconductor package technology and, more particularly, to techniques for designing bypass capacitive structures between power and ground rails of a semiconductor package.
2. Description of the Related Art
As device operating speeds and the slew rates of driver switching simultaneously increase, the quality of the power V.sub.dd and ground V.sub.ss routing systems become a critical factor in the overall integrity of the system. In current designs, providing a source of charge in close vicinity of the switching activity is essential for the proper functioning of an overall integrated circuit system.
In the prior art, a common way of providing a reservoir of charge near switching circuitry (i.e., I/O driver circuitry) has been to mount discrete capacitive components between the power V.sub.dd and the ground V.sub.ss lines. As a result, prior art system have been able to somewhat improve a system's electrical performance. These discrete capacitors are usually mounted on a package substrate and then directly interconnected to the power V.sub.dd and ground V.sub.ss through conductive leads and vias.
However, a major problem with using discrete capacitors to decouple the system V.sub.dd and V.sub.ss lines is that they lose their effectiveness at high frequencies. Furthermore, there is often not enough space on the semiconductor package surface to mount a larger number of discrete capacitors that may be necessary to decouple the system.
An example of a typical semiconductor package is shown in FIG. 1A. FIG. 1A shows a semiconductor package 100 having a package substrate 102. A semiconductor chip 104 is mounted on the package substrate 102. A plurality of conductive traces 106 are routed on the package substrate 102. A ground rail V.sub.ss ring 108 is routed on the package substrate 102 and connected to the semiconductor chip 104 by a plurality of bond wires 105a. A power rail V.sub.dd ring 110 is also routed on the package substrate 102 and connected to the semiconductor chip 104 by another plurality of bond wires 105b.
For ease of illustration, only four bond wires are shown, but as is well known in the art, many more bond wires 105a and 105b are used to provide appropriate connections between semiconductor chip 104 and ground rail ring V.sub.ss 108 and power rail V.sub.dd ring 110. A discrete capacitor 112 having conductive leads 114a and 114b is mounted to the package substrate 102. In this example, only two discrete capacitors are shown mounted on the package substrate 102. However, in order to provide sufficient charge near driver circuits of the semiconductor chip 104, many more discrete capacitors 112 should be mounted on the package substrate 102.
Although more discrete capacitors 112 can be added to the package substrate 102, because discrete capacitors 112 are relatively large components, there is typically not enough space on the package substrate 102 surface to mount the number of discrete capacitors 112 necessary to provide a sufficiently close charge storage location and an adequate level of decoupling for the power V.sub.dd and ground V.sub.ss lines. As will be discussed further below, the conductive leads 114a and 114b may also exhibit unacceptably high levels of impedance at high frequencies, which necessarily reduce the effectiveness of the discrete capacitors 112.
FIG. 1B is a cross-sectional view A--A of FIG. 1A, which illustrates the respective layers of the semiconductor package 100. The packaging substrate 102 is made up of several layers including solder balls 116, a power plane V.sub.dd 118, a ground plane V.sub.ss 122 and dielectric layers 119, 120 and 124. Conductive leads 114a and 114b are connected to conductive vias 126 and 128. In the same manner, bond wires 105a and 105b are connected to conductive vias 130 and 132. The conductive vias 126 and 132 are defined through the dielectric layer 124 and connect to the ground plane V.sub.ss 122. In the same manner, the conductive vias 128 and 130 are defined through the ground plane V.sub.ss 122 and dielectric layers 120 and 124 to connect to the power plane V.sub.dd 118.
FIG. 1C shows a simplified partial top view of a ground rail V.sub.ss ring 108 and a power rail V.sub.dd ring 110 with their respective conductive vias 130 and 132. In this manner, the semiconductor chip 104 is able to interconnect to the ground plane V.sub.ss 122 and the power plane V.sub.dd 118 through respective bond wires 105a and 105b.
As can be appreciated even more in FIG. 1B, only a limited number of discrete capacitors 112 can be mounted onto the packaging substrate 102. Conductive leads 114a and 114b with their respective vias 126 and 128 define conductive paths to the power plane V.sub.dd 118 and the ground plane V.sub.ss 122. These paths exhibit high impedance at high frequencies. Therefore, conventional devices are generally not able to provide low impedance paths between the power plane V.sub.dd 118 and the ground plane V.sub.ss 122.
Another problem with the use of conventional discrete capacitive components is that on-chip driver circuitry, which is required to switch at fast speeds, typically accesses an amount of charge that is stored in the discrete capacitors 112. Unfortunately, the distance between the discrete capacitors 112 and a selected on-chip driver circuit will be different, depending on the placement of the discrete capacitor on the package substrate. As is well known, as the distance between the driver circuitry and the stored charge increases, the speed at which on-chip driver circuitry (and other circuit components) operates will necessarily slow down. This therefore detrimentally impacts on the performance on any semiconductor chip 104 that may be mounted on the package.
In view of the foregoing, it is desirable to have a method and apparatus that provides for a low impedance path between the power V.sub.dd and ground V.sub.ss lines , and remain efficient at high frequency. It is also desirable to have a device that can be installed easily into the semiconductor package without being limited to the space available on the package substrate.